The transition from aluminum to copper in integrated circuit (IC) fabrication required a change in process “architecture” (to damascene and dual-damascene) as well as a whole new set of process technologies. One process step used in producing copper damascene circuits is the formation of a “seed-” or “strike-” layer, which is then used as a base layer onto which copper is electroplated (“electrofill”). The seed layer carries the electrical plating current from the edge region of the wafer (where electrical contact is make) to all trench and via structures located across the wafer surface. The seed film is typically a thin conductive copper layer. It is separated from the insulating silicon dioxide or other dielectric by a barrier layer. The seed layer deposition process should yield a layer which has good overall adhesion, excellent step coverage (more particularly, conformal/continuous amounts of metal deposited onto the side-walls of an embedded structure), and minimal closure or “necking” of the top of the embedded feature.
Market trends of increasingly smaller features and alternative seeding processes drive the need for a capability to plate with a high degree of uniformity on increasingly thin seeded wafers. In the future, it is anticipated that the seed film may simply be composed of a plateable barrier film, such as ruthenium, or a bilayer of a very thin barrier and copper (deposited, for example, by an atomic layer deposition (ALD) or similar process). These films present the engineer with an extreme terminal effect situation. For example, when driving a 3 amp total current uniformly into a 30 ohm per square ruthenium seed layer (a likely value for a 30-50 Å film) the resultant center to edge voltage drop in the metal will be over 2 volts. To effectively plate a large surface area, the plating tooling makes electrical contact to the conductive seed only in the edge region of the wafer substrate. There is no direct contact made to the central region of the substrate. Hence, for highly resistive seed layers, the potential at the edge of the layer is significantly greater than at the central region of the layer. Without appropriate means of resistance and voltage compensation, this large edge-to-center voltage drop could lead to an extremely non-uniform plating thickness distribution, primarily characterized by thicker plating at the wafer edge. For comparison, the thermodynamic limit of the voltage drop for electrolyte solvent (water) is only about 1.4V.
FIG. 1 is a schematic of an approximated equivalent electrical circuit for the problem. It is simplified to one dimension for clarity. The continuous resistance in the seed layer is represented by a set of finite (in this case four) parallel circuit elements. The in-film resistor elements Rf, represent the differential resistance from an outer radial point to a more central radial point on the wafer. The total current supplied at the edge, It is distributed to the various surface elements, I1, I2, etc., scaled by the total path resistances with respect to all the other resistances. The circuits more centrally located have a larger total resistance because of the cumulative/additive resistance of the Rf for those paths. Mathematically, the fractional current Fi through any one of the surface element paths is
                              F          i                =                                            I              i                                      I              t                                =                                                    Z                T                                            Z                i                                      =                                          1                                  (                                                            iR                      f                                        +                                          R                                              ct                        ,                        i                                                              +                                          Zw                      i                                        +                                          R                                              el                        ,                        i                                                                              )                                                                              ∑                  1                  n                                ⁢                                  1                                                            iR                      f                                        +                                          R                                              ct                        ,                        i                                                              +                                          Zw                      i                                        +                                          R                                              el                        ,                        i                                                                                                                                                    (        1        )            
where n is the total number of parallel paths that the circuit is divided into, i (sometime used as a subscript) refers to the ith parallel current path (from the edge terminal), t refers to the total circuit, I is current, Rf is the resistance in the metal film between each element (constructed, for simplicity, to be the same between each adjacent element), Rct is the local charge transfer resistance, Zw is the local diffusion (or Warberg) impedance and Rel is the electrolyte resistance. With this, Ii is the current to through the ith surface element pathway, and It is the total current to the wafer. The charge transfer resistance at each interfacial location is represented by a set of resistors Rct in parallel with the double layer capacitance Cdl, but for the steady state case does not effect the current distribution. The diffusion resistances, represented by the Warberg impedance (symbol Zw) and the electrolyte resistance (Rel) are shown in a set of parallel circuit paths, all in series with the particular surface element circuit, give one of several parallel paths for the current to traverse to the anode. In practice, Rct and Zw are quite non-linear (depending on current, time, concentrations, etc.), but this fact does not diminish the utility of this model in comparing how the current art and this disclosure differ in accomplishing uniform current distribution. To achieve a substantially uniform current distribution, the fractional current should be the same, irrespective of the element position (i). When all terms other than the film resistance term, Rf, are relatively small, the current to the ith element is
                    F        =                              1            i                                              ∑              1              n                        ⁢                          1              i                                                          (        2        )            
Equation 2 has a strong i (location) dependence and results when no significant current distribution compensating effects are active. In the other extreme, when Rct, Zw, Rel or the sum of these terms are greater than Rf, the fractional current approaches a uniform distribution; the limit of equation 1 as these parameters become large is F=1/n, independent of location i.
Classical means of improving plating non-uniformity draw upon (1) increase Rct through the use of copper complexing agents or charge transfer inhibitors (e.g., plating suppressors and levelers, with the goal of creating a large normal-to-the-surface voltage drop, making Rf small with respect to Rct), (2) very high ionic electrolyte resistances (yielding a similar effect through Rel), (3) creating a significant diffusion resistance (Zw), or (4) variations of a plating current recipe to minimize voltage drop, or control of mass transfer rate to limit current density in areas of high interfacial voltage drop (see e.g., U.S. Pat. Nos. 6,110,346, 6,074,544, and 6,162,344, each of which is incorporated herein by reference).
These approaches have significant limitations related to the physical properties of the materials and the processes. Typical surface polarization derived by organic additives cannot create polarization in excess of about 0.5V (which is a relatively small value in comparison to, for example, the 2V seed layer voltage drop that must be compensated as noted above). Also, because the conductivity of a plating bath is tied to its ionic concentration and pH, decreasing the conductivity directly and negatively impacts the rate of plating and morphology of the plated material.
What is needed therefore is an improved technique for uniform electroplating onto thin-metal seeded wafers, particularly wafers with large diameters (e.g. 300 mm).
In a separate but related aspect, there is a need for developing a wafer-to-electrolyte entry process that is compatible with techniques used for uniform electroplating. This is important because conditions used during immersion of a wafer into electrolyte largely determine success of subsequent plating. In general, entry of a wafer carrying a thin seed layer into electrolyte can lead to a number of serious performance and feature filling issues if entry is not properly controlled (see for example, U.S. Pat. No. 6,946,065, which is herein incorporated by reference in its entirety and for all purposes.).
Wafer entry can fall into three major process classes: cold, hot and potentiostatic. In cold entry, polarization and plating of the wafer is delayed until the wafer entry into electrolyte is complete. Because of corrosive nature of electrolyte, delayed wafer polarization can result in seed layer corrosion and formation of voids at the bottoms of the features. In hot entry, the wafer is polarized prior to or during entry such that the total current requested of the power supply is substantially fixed and, therefore, current density experienced by the wafer during entry into electrolyte depends on the area of wetted portions of the wafer. The current density is greatest (and is often excessive) at the beginning of wafer immersion, when the area of wetted wafer surface is small. As the immersion proceeds further and as larger area of the wafer becomes wetted, the current density experienced by the wafer becomes smaller. Hot entry is superior to cold entry in general, but because current density is starting at a high level and is ending at a low level and because the differences between these can be very substantial, either wafer burning (at high current density) or seed layer corrosion (at low current density) can occur.
In potentiostatic entry the potential between the wafer and a reference electrode carrying no current, is maintained at a fixed value and the current increases approximately linearly with increasing wetted area of the wafer.
With the development of methods and apparatus for reducing the terminal effect, it becomes increasingly important to choose the best compatible wafer entry method, and to adapt it for use with the newly developed system for uniform plating.